/*
 * Copyright (C) 2024, Ingenic Semiconductor Co.,Ltd.
 * Author: Keven <keven.ywhan@ingenic.com>
 */

#ifndef __SPL_CONFIG_H__
#define __SPL_CONFIG_H__

#define CONFIG_FPGA_TEST
#define CONFIG_EXTAL_CLK_HZ	24000000
#define CONFIG_CPU_CLOCK_HZ	100000000
#define CONFIG_SPL_MMC_SUPPORT

/* UART CONFIG START */
#define CONFIG_UART_INDEX	1
#define CONFIG_UART_BAUDRATE	115200
#define CONFIG_UART_CLK_HZ	24000000
/* UART CONFIG END */

/* MMC CONFIG START */
#define CONFIG_MSC_INDEX	0
#define MSC_BUS_WIDTH_1		0
#define MSC_BUS_WIDTH_4		1
#define MSC_BUS_WIDTH		(MSC_BUS_WIDTH_4)
#define MSC_BLOCK_SIZE		(512)
#define GPT_TABLE_SIZE		(17 * 1024)
/* MMC CONFIG END */

/* SFC CONFIG START */
#define CONFIG_SFC_INDEX	0
#define SFC_NOR                 0
#define SFC_NAND                1
#define SFC_XIP                 2
#define CONFIG_SFC_TYPE         (SFC_NOR)
#define SFC_BLOCK_SIZE          (512)
/* SFC CONFIG END */

#define RAM_TYPE_DDR3           (1)
#define RAM_TYPE_DDR4           (2)
#define RUNNING_RAM_TYPE        (RAM_TYPE_DDR3)

#define CONFIG_SPL_MAX_SIZE	(32 * 1024)
#define CONFIG_SPL_TEXT_BASE	0x12604000
#define CONFIG_SYS_TEXT_BASE	0x80000000
#define CONFIG_SYS_MAX_SIZE	(128 * 1024)
#define CONFIG_SYS_OFFSET	(GPT_TABLE_SIZE + CONFIG_SPL_MAX_SIZE)

#endif /* __SPL_CONFIG_H__ */

